A processor generally has associated with it an instruction pipeline which includes fetching, decoding (or dispatching) and executing stages. The decoding stage retrieves an instruction from a fetch queue. If the fetched instruction is a store operation, queue entries are allocated in arithmetic logic unit (ALU) scheduler queues (ALSQs), address generation scheduler queues (AGSQs) and store queues (STQs). Conventional processors perform one store operation per cycle. In an effort to increase the instructions per cycle (IPC), some processors use a two-store commit architecture. This is done at the cost of additional control logic on the die area and increased power usage.